Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

作     者：S.V.Ratankumar L.Koteswara Rao M.Kiran Kumar 

作者机构：Department of Electronics and Communication EngineeringKoneru Lakshmaiah Education FoundationAziz NagarHyderabad500075TelanganaIndia Department of Electronics and Communication EngineeringRGM College of Engineering and TechnologyNandyal518501Andhra PradeshIndia Department of Electrical and Electronics EngineeringKoneru Lakshmaiah Education FoundationVaddeswaramGuntur522502Andhra PradeshIndia 

出 版 物：《Computers, Materials & Continua》 (计算机、材料和连续体（英文）)

年 卷 期：2022年第73卷第12期

页      面：5283-5298页

核心收录：

学科分类：0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0703[理学-化学] 0811[工学-控制科学与工程] 0701[理学-数学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Carbon nanotube field effect transistor(CNTFET) multivalued logic(MVL) ternary adder Hewlett simulation program with integrated circuit emphasis(HSPICE) chirality(nm) adder 

摘      要：The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.