Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

作     者：Reeya Agrawal Anjan Kumar Salman A.AlQahtani Mashael Maashi Osamah Ibrahim Khalaf Theyazn H.H.Aldhyani 

作者机构：VLSI Center of ExcellenceGLA UniversityMathura281406India Computer Engineering DepartmentResearch Chair of New Emerging Technologies and 5G Networks and BeyondCollege of Computer and Information SciencesKing Saud UniversitySaudi Arabia Software Engineering DepartmentKing Saud UniversityRiyadh11543Saudi Arabia Al-Nahrain UniversityAl-Nahrain Nano-Renewable Energy Research CenterBaghdadIraq Applied College in AbqaiqKing Faisal UniversityAl-Ahsa31982Saudi Arabia 

出 版 物：《Computers, Materials & Continua》 (计算机、材料和连续体（英文）)

年 卷 期：2022年第73卷第11期

页      面：2313-2331页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Research General Direction funded this research at Universidad Santiago de Cali Grant Number 01-2021 and APC was funded by 01-2021 

主　　题：Current differential sense amplifier(CDSA) voltage differential sense amplifier(VDSA) voltage latch sense amplifier(VLSA) current latch sense amplifier(CLSA) charge-transfer differential sense amplifier(CTDSA) new emerging technologies 

摘      要：Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the *** of the time,these caches are made of static random access memory *** take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several *** is true for phones and *** memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of *** conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier ***,power reduction techniques are applied over different blocks of cache memory architecture to optimize *** single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.