Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

作     者：张甲 杨海钢 孙嘉斌 余乐 韦援丰 

作者机构：Institute of Electronics Chinese Academy of Sciences University of Chinese Academy of Sciences 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2014年第35卷第8期

页      面：121-127页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0703[理学-化学] 0702[理学-物理学] 

基　　金：Project supported by the National Natural Science Foundation of China(No.61271149) the CAS/SAFEA International Partnership Program for Creative Research Teams 

主　　题：electrostatic discharge enclosed-gate layout transistor modeling conformal mapping 

摘      要：This paper proposes a novel technique for modeling the electrostatic discharge （ESD） characteristic of the enclosed-gate layout transistors （ELTs）. The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELF is decomposed into edge and comer transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM （Berkeley Short- channel IGFET Model）. Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.