An I/Q DAC with gain matching circuit for a wireless transmitter

作     者：汤华莲 庄奕琪 景鑫 张丽 

作者机构：Ministry of Education Key Laboratory of Wide Band-Gap Semiconductor Materials and DeviceXidian University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2013年第34卷第6期

页      面：126-131页

核心收录：

学科分类：0810[工学-信息与通信工程] 080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 081001[工学-通信与信息系统] 

基　　金：supported by the National Science and Technology Major Projects of China(No.2010ZX03002-001-02) the Fundamental Research Funds for the Central Universities(No.K50511250006) 

主　　题：digital-to-analog converter gain mismatch switch current cell 

摘      要：This paper presents a two-channel 12-bit current-steering digital-to-analog converter（DAC） for I and Q signal paths in a wireless *** proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA.A gain matching circuit is proposed to reduce gain mismatch between the I and Q *** tuning range is±24%of full scale and the minimum resolution is 1/16 *** further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch *** chip has been processed in a standard 0.13μm CMOS *** mismatch between a 1-channel DAC and a Q-channel DAC is measured to be approximately 0.13%.At 120-MSPS sample rate for 1 MHz sinusoidal signal,the spurious free dynamic range （SFDR） is 75 *** total power dissipation is 62 mW and has an active area of 1.08 mm^2.