Optimizing the thickness of Ta_(2)O_(5) interfacial barrier layer to limit the oxidization of Ta ohmic interface and ZrO_(2) switching layer for multilevel data storage

作     者：Muhammad Ismail Haider Abbas Chandreswar Mahata Changhwan Choi Sungjun Kim Muhammad Ismail;Haider Abbas;Chandreswar Mahata;Changhwan Choi;Sungjun Kim

作者机构：Division of Electronics and Electrical EngineeringDongguk UniversitySeoul 04620Republic of Korea Division of Materials Science and EngineeringHanyang UniversitySeoul 04763Republic of Korea 

出 版 物：《Journal of Materials Science & Technology》 (材料科学技术（英文版）)

年 卷 期：2022年第106卷第11期

页      面：98-107页

核心收录：

学科分类：07[理学] 070205[理学-凝聚态物理] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 081201[工学-计算机系统结构] 0702[理学-物理学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No.2021R1C1C1004422) the Dongguk University Research Fund of 2020 supported through the National Research Foundation of Korea (NRF) funded by the Ministry of Science,ICT & Future Planning (Nos.NRF2020M3F3A2A02082449 and NRF-2016R1A6A1A03013422) 

主　　题：Resistive switching Ta_(2)O_(5)/ZrO_(2)bilayer film Barrier layer thickness Multilevel resistance states RESET-stop voltage 

摘      要：The multilevel storage capability of nonvolatile resistive random access memory(ReRAM)is greatly de-sired to accomplish high functioning memory *** this study,Ta_(2)O_(5) thin film with different thick-nesses(2,4,and 6 nm)was exploited as an appropriate interfacial barrier layer for limiting the formation of the interfacial layer between the 10 nm thick sputtering deposited resistive switching(RS)layer and Ta ohmic electrode to improve the switching cycle endurance and *** show that lower form-ing voltage,narrow distribution of SET-voltages,good dc switching cycles(10^(3)),high pulse endurance(10^(6) cycles),long retention time(10^(4) s at room temperature and 100℃),and reliable multilevel resis-tance states were obtained at an appropriate thickness of∼2 nm Ta_(2)O_(5) interfacial barrier layer instead of without Ta_(2)O_(5) and with∼4 nm,and∼6 nm Ta_(2)O_(5) barrier layer,ZrO_(2)-based memristive ***,multilevel resistance states have been scientifically investigated via modulating the compliance current(CC)and RESET-stop voltages,which displays that all of the resistance states were distinct and stayed stable without any considerable deprivation over 10^(4) s retention time and 104 pulse endurance *** I-V characteristics of RESET-stop voltage(from−1.7 to−2.3 V)of HRS are found to be a good linear fit with the Schottky *** can be seen that Schottky barrier height rises by increasing the stop-voltage during RESET-operation,resulting in enhancing the data storage memory window(on/offratio).Moreover,RESET-voltage and CC control of HRS and LRS revealed the physical origin of the RS mecha-nism,which entails the formation and rupture of conducting *** is thoroughly investigated that proper optimization of the barrier layer at the ohmic interface and the switching layer is essential in memristive *** results demonstrate that the ZrO_(2)-based memristive device with an optimized∼2 nm Ta_(2)O_(5) barrier