Hardware for multi-superconducting qubit control and readout

作     者：Zhan Wang Hai Yu Rongli Liu Xiao Ma Xueyi Guo Zhongcheng Xiang Pengtao Song Luhong Su Yirong Jin Dongning Zheng 王战;于海;刘荣利;马骁;郭学仪;相忠诚;宋鹏涛;苏鹭红;金贻荣;郑东宁

作者机构：Institute of PhysicsChinese Academy of SciencesBeijing 100190China Beijing Academy of Quantum Information SciencesBeijing 100193China Beijing Liuhe Lianchuang Technology Co.Ltd.Beijing 100011China University of Chinese Academy of SciencesBeijing 100049China Songshan Lake Materials LaboratoryDongguan 523808China 

出 版 物：《Chinese Physics B》 (中国物理B（英文版）)

年 卷 期：2021年第30卷第11期

页      面：214-222页

核心收录：

学科分类：080902[工学-电路与系统] 07[理学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 070201[理学-理论物理] 0702[理学-物理学] 

基　　金：Project supported by the State Key Development Program for Basic Research of China(Grants Nos.2017YFA0304300 and 2016YFA0300600) the Natural Science Foundation of Beijing,China(Grant No.Z190012) the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2020B0303030001) the Strategic Priority Research Program of Chinese Academy of Sciences(Grant No.XDB28000000) 

主　　题：superconducting qubit dispersive readout arbitrary-waveform generator(AWG) analog-digital converter(ADC) 

摘      要：We have developed an electronic hardware system for the control and readout of multi-superconducting qubit *** hardware system is based on the design ideas of good scalability,high synchronization and low *** system,housed inside a VPX-6U chassis,includes multiple arbitrary-waveform generator(AWG)channels,analog-digital-converter(ADC)channels as well as direct current source *** system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis,and control and readout of more and more qubit can be carried out by interconnecting the *** using field programmable gate array(FPGA)processors,the system incorporates three features that are specifically useful for superconducting qubit ***,qubit signals can be processed using the on-board FPGA after being acquired by ADCs,significantly reducing data processing time and data amount for storage and ***,different output modes,such as direct output and sequential output modes,of AWG can be implemented with pre-encoded ***,with data acquisition ADCs and control AWGs jointly controlled by the same FPGA,the feedback latency can be reduced,and in our test a 178.4 ns latency time is *** is very useful for future quantum feedback ***,we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.