A BCH error correction scheme applied to FPGA with embedded memory

作     者：Yang LIU Jie LI Han WANG Debiao ZHANG Kaiqiang FENG Jinqiang LI Yang LIU;Jie LI;Han WANG;Debiao ZHANG;Kaiqiang FENG;Jinqiang LI

作者机构：National Key Laboratory for Electronic Measurement TechnologyNorth University of ChinaTaiyuan 030051China Shandong Aerospace Electronic Technology InstituteYantai 264000China 

出 版 物：《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿（英文版）)

年 卷 期：2021年第22卷第8期

页      面：1127-1139页

核心收录：

学科分类：0810[工学-信息与通信工程] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 0839[工学-网络空间安全] 08[工学] 0835[工学-软件工程] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project supported by the National Natural Science Foundation of China(No.61973280) the China Postdoctoral Science Foundation(No.2019M661069) 

主　　题：Error correction algorithm Bose-Chaudhuri-Hocquenghem(BCH)code Field programmable gate array(FPGA) NAND flash 

摘      要：Given the potential for bit flipping of data on a memory medium,a high-speed parallel Bose-Chaudhuri-Hocquenghem(BCH)error correction scheme with modular characteristics,combining logic implementation and a look-up table,is *** is suitable for data error correction on a modern field programmable gate array full with on-chip embedded *** elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.