Efficient Scheduling Mapping Algorithm for Row Parallel Coarse-Grained Reconfigurable Architecture

作     者：Naijin Chen Zhen Wang Ruixiang He Jianhui Jiang Fei Cheng Chenghao Han Naijin Chen;Zhen Wang;Ruixiang He;Jianhui Jiang;Fei Cheng;Chenghao Han

作者机构：School of Computer and Information ScienceAnhui Polytechnic UniversityWuhu 241000China School of Computer Science and TechnologyShanghai University of Electric PowerShanghai 200090China School of Software EngineeringTongji UniversityShanghai 201804China 

出 版 物：《Tsinghua Science and Technology》 (清华大学学报（自然科学版（英文版）)

年 卷 期：2021年第26卷第5期

页      面：724-735页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 081202[工学-计算机软件与理论] 

基　　金：supported by the Natural Science Foundation of Anhui Province(No.1808085MF203) the National Natural Science Foundation of China(No.61432017)。 

主　　题：temporal mapping Reconfigurable Cell Array(RCA) listed scheduling communication costs 

摘      要：Row Parallel Coarse-Grained Reconfigurable Architecture(RPCGRA)has the advantages of maximum parallelism and programmable flexibility.Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints.To solve this problem,the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA.In this paper,we present a Depth-First Greedy Mapping(DFGM)algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array(RCA).Compared with level breadth mapping,the performance of DFGM is better.The percentage of maximum improvement in the use times of RCA is 33%and the percentage of maximum improvement in non-original input and output times is 64.4%(Given Discrete Cosine Transfor 8(DCT8),and the area of reconfigurable processing unit is 56).Compared with level-based depth mapping,DFGM also obtains the lowest averages of use times of RCA,non-original input and output times,and the reconfigurable time.