A9.8-30.1GHzCMOSlow-noise amplifier with a 3.2-dB noise figure using inductor-and transformer-based gm-boosting techniques
[基于电感和变压器跨导提升技术、噪声系数为3.2dB、 带宽为9.8–30.1GHz的CMOS低噪声放大器]作者机构:Guangdong Provincial Key Laboratory of Millimeter-Wave and TerahertzSchool of Electronic and Information EngineeringSouth China University of TechnologyGuangzhou 510641China School of Science and EngineeringThe Chinese University of Hong KongShenzhenShenzhen 518172China
出 版 物:《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿(英文版))
年 卷 期:2021年第22卷第4期
页 面:586-598页
核心收录:
学科分类:080902[工学-电路与系统] 0809[工学-电子科学与技术(可授工学、理学学位)] 08[工学]
基 金:Project supported by the National Key R&D Program of China(No.2018YFB1802000) the Key-Area R&D Program of Guangdong Province,China(No.2018B010115001) the Guangdong Innovative and Entrepreneurial Research Team Program,China(No.2017ZT07X032)
主 题:CMOS gm-boosting Low-noise amplifier Transformer Common-gate
摘 要:A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is *** the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for simultaneous wideband input matching and relatively high *** the circuit level,multiple techniques are proposed to improve LNA ***,in the CG stage,loading effect is properly used instead of the conventional feedback technique,to enable simultaneous impedance and noise ***,based on in-depth theoretical analysis,the inductor-and transformer-based gm-boosting techniques are employed for the CG and CS stages,respectively,to enhance the gain and reduce power ***,the floating-body method,which was originally proposed to lower NF in CS amplifiers,is adopted in the CG stage to further reduce *** in a 65-nm CMOS technology,the LNA chip occupies an area of only 0.2 mm^(2)and measures a maximum power gain of 10.9 dB with−3 dB bandwidth from 9.8 to 30.1 *** NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire *** LNA consumes 15.6 mW from a 1.2-V supply.