A Stoppable Clock Based Four Step Search Block-Matching Motion Estimation Architecture

作     者：Salah Dhahri Abdelkrim Zitouni Kholdoun Torki 

作者机构：Electronic and Micro-Electronic Laboratory Faculty of Sciences of Monastir Monastir 5000 Tunisa Circuits Multi-Project 46 Avenue Felix Viallet Grenoble Cedex 38031 France 

出 版 物：《Computer Technology and Application》 (计算机技术与应用（英文版）)

年 卷 期：2011年第2卷第7期

页      面：570-574页

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 081203[工学-计算机应用技术] 08[工学] 0835[工学-软件工程] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：H264 four step search power consumption motion estimation. 

摘      要：Motion Estimation （ME） is considerate one of the most important compression methods. However, ME involves high computational complexity. The main goal is to reduce power conception and the execution time without reducing image quality. In this paper, the authors have proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method is based on the stoppable clock models. The architecture has been simulated and synthesized with VHDL and ASIC （CMOS 45 nm）. Synthesize results show that the proposed architecture reduces the power consumption and achieves a high performance for real time motion estimation.